In the fabrication of semiconductor packages, the semiconductor die or chip is frequently attached to an underlying pad, which may be used for electrical and/or thermal purposes. An example is shown in FIGS. 1A and 1B, which is a cross-sectional view and a top view, respectively of a semiconductor chip package 10. FIG. 1A is taken at cross section 1A—1A shown by the dashed line in FIG. 1B. In package 10, a semiconductor die 102 is attached to a die pad 104 by means of a nonconductive epoxy layer 106. Pins 108, 110 and 112 extend from package 10, pins 108 and 100 being separate from die pad 104 and pin 112 being integral with die pad 104. Pads 108a and 110a on the top surface of die 102 are connected to pins 108 and 110 with wires 108b and 110b, respectively. A pad 112a on the top surface of die 102 is connected to die pad 104 with a wire 112b. In this embodiment, pin 108 is connected to a first voltage rail, Vcc, and pin 110 is connected to a second voltage rail, Vdd or ground. Pin 112 is a function pin.
Die pad 104 and pins 108, 110 and 112 are typically plated with silver or a silver alloy.
The lower portion of die 102, which is adjacent to die pad 104, is frequently doped with a P-type impurity (such as boron) or an N-type impurity (such as phosphorus or arsenic) to provide the required electrical circuitry within die 102. Die 102 and die pad 104 are often biased at different electrical potentials. For example, if the lower portion of die 102 is doped with a P-type impurity, die 102 will normally be biased negative with respect to die pad 104. Conversely, if the lower portion of die 102 is doped with an N-type impurity, die 102 will normally be biased positive with respect to die pad 104.
A problem may occur if a leakage current develops between die 102 and die pad 104, for example at a leakage path 114, shown in FIG. 1A. This can happen by electrochemical migration. Leakage path 114 indicates a leakage between the function pin 112 and the voltage on the backside of die 102, which in this example is Vdd or ground. This leakage current is particularly troublesome if the lower portion of die 102 is biased negative with respect to die pad 104. In that event, positively charged silver ions (Ag+) from the plating on die pad 104 tend to migrate to die 102, where they combine with electrons and are deposited as silver metal. The leakage current tends to interfere with the output on pin 112.
This problem is less severe when the lower portion of die 102 is biased positive with respect to die pad 104.
The problem of silver migration could be reduced if the thickness of the nonconductive epoxy layer 106 were increased. This is difficult with the existing technology, however, as will be explained with reference to FIGS. 2A–2E.
FIGS. 2A–2E illustrate a conventional process for forming a semiconductor package, particularly the manner in which the nonconductive epoxy layer is applied. FIG. 2A shows a semiconductor wafer 20 being separated into dice or chips 21 with a dicing saw 22. FIG. 2B shows a liquid nonconductive epoxy layer 23 being applied to the backside of one of dice 21 with a dispensing needle 24. FIG. 2C shows the structure after die 21 has been attached to a die pad 25. FIG. 2D shows the structure after bonding wires 26 have connected pads on the top side of die 21 to points on die pad 25. FIG. 2E shows the completed package after die 21 and bonding wires 26 have been encased in a molding compound 27.
The problem with this process is that the dispensed nonconductive epoxy 23 is in a liquid form. It is very difficult to control the set up of the epoxy so as to produce a thick layer, while preventing the epoxy from bleeding and overflowing the edges of die pad 25, particularly if die 21 is about the same size as die pad 25.
Accordingly, there is a need for a method of reliably providing a thick layer of nonconductive epoxy between the die and die pad to prevent a leakage current between the die and die pad.